发明名称 LOGICAL OPERATION CIRCUIT TESTING UNIT
摘要 PURPOSE:To facilitate a test for a large-scale logical operation circuit by providing a means which applies test data to the output pin in a high-impedance state of a tri- state element in the ligical operation circuit. CONSTITUTION:Logical operation circuit 1 consists of IC 3 mounted on IC board 2, tri-state element 4 which can take a high-impedance state besides binary states, external input terminal 5, external output terminal 6, output pin 7 in the high-impedance state of tri-state element 4, observation point 8 and clock terminal 9. The test pattern stored in testpattern storage circuit 19 is applied to output pin 7, and the operation result of logical operation circuit 1 for the test pattern above is read from external output terminal 6 or observation point 8 and is sent to output comparator circuit 17 through I/0 control circuit 14 and is compared with a correct solution value.
申请公布号 JPS5549761(A) 申请公布日期 1980.04.10
申请号 JP19780122245 申请日期 1978.10.03
申请人 NIPPON ELECTRIC CO 发明人 WAKATSUKI NOBUO
分类号 G01R31/28;G01R31/317;G06F11/00;G06F11/22 主分类号 G01R31/28
代理机构 代理人
主权项
地址