| 摘要 |
<p>PURPOSE:To make it possible to incorporate a facsimile-terminal circuit in a packet multiplier without alteration, by connecting a control circuit, which controls facsimile terminals, to the direct memory access bus line of a processor in the packet multiplier. CONSTITUTION:Facsimile terminal control circuit 10 which controls facsimile terminals consists of control circuit 18, a reception part and transmission part. To send out packeted data in processor 2 to facsimile terminal 11, the number of bytes equivalent to the volume of data in each packet is set to transmitting byte counter 12, and an initial address to be sent is to address counter 13. Control circuit 18 stores packeted data in buffer memory 14 and sequentially reads and sends them to terminal 11. To receive them, processor 2 sets fixed values to receiving byte counter 15 and address counter 16 facsimile signal from terminal 11 through reception signal line 20 is stored in buffer memory 17 after series-parallel conversion, and then sent to processor 2 through data bus 3.</p> |
