发明名称 TIMING PHASE SYNCHRONIZATION SYSTEM
摘要 PURPOSE:To attain high-speed synchronous drawing by increasing a sampling frequency by additionally inserting a sampled value of zero into sampling outputs of timing signal components. CONSTITUTION:Reference frequency (fo) is sent to divider 3 by way of divider circuit 1 and pulse control circuit 2 to form sampling pulse (fs). A timing signal component of frequency (ft), on the other hand, is sampled 4 and then applied to sample interpolation circuit 5, which inserts the (k-)-number sampled values into sampled values in each period of 1/fs. Then, timing component extraction circuit 6 with a narrow-band filter removes noises, etc., so that the output of circuit will be a timint signal of sampling frequency kfs. In this way, a zero cross point is detected 7 at a high speed, the needed number of shift pulses is set 8 and circuit 2 samples output pulses of divider circuit 1. In this way, synchronous drawing can be performed at a high speed.
申请公布号 JPS5546628(A) 申请公布日期 1980.04.01
申请号 JP19780119677 申请日期 1978.09.28
申请人 FUJITSU LTD 发明人 MURANO KAZUO;HAYASHI TATSUKI;UMIGAMI SHIGEYUKI;AMANO FUMIO;ITOU YASUKAZU
分类号 H04L7/033 主分类号 H04L7/033
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