| 摘要 |
PURPOSE:To make a decision on an error without waiting the read end of data by adding an error sample display bit to each PCM regenerated signal data in write operation of a memory for time-axis elongation and then by reading data with this bit at its initial. CONSTITUTION:Once a clock is inputted, counter 35 generates a high-level output until a bit corresponding to data of a regenerated PCM signal and counter 36 applied with the clock writes data in RAM 24; when data bits end and the output of counter 35 is inverted, counter 36 stops. On the other hand, parity detection circuit 35 outputs a parity check result to a bit counted by a fixed number from the write end of RAM 24 and at the same time, counter 35 is reset to write the parity check result at the zero address of RAM 24 while data are written from the 1st address. At the time of a read from memory 24, error data added to the initial bit of each data is read out without waiting the read end of data, so that an elongated-PCM signal processing circuit following RAM will be simple. |
