| 摘要 |
PURPOSE:To increase the time region enable for the order re-execution and thus to increased the reliability for the device by cancelling all writing holding bits when the order execution control circuit detects the end of the order process and then restart the writing request to the memory device. CONSTITUTION:Writing data buffer circuit 212 holds temporarily the writing data and address at the data writing time from CPU200 to memory device 201. Here writing data buffer control circuit 230 holds the writing request to device 201 in case writing holding bit 233 is set although writing data effective bit 234 is set up, and gives queuing until bit 233 is cancelled. After this, when order execution control circuit 221 detects the end of the order process, writing holding bit cancel circuit 232 cancels the full bit of bit 233 to start again writing request 249 to device 201. Thus the time region enable for the order re-execution can be increased, thus enhancing the reliability for the device. |
