| 摘要 |
PURPOSE:To obtain a logic arithmetic unit which can process the Boolean algebra containing the parenthesis order in a short time and simple constitution. CONSTITUTION:Receiving 1st timing signal T1, 1st temporary memory means IRG memorizes temporarily the input information at that time point and then delivers it. In case the closing parenthesis order is received, the input information at the generating time of 2nd timing signal T2 is memorized temporarily and then delivered. Receiving 4th timing signal T4, 2nd and 3rd temporary memory parts ARG and ORG memorize temporarily the input information at that time point and deliver it. In case the open parenthesis order is received, the input information at the generating time point of 3rd timing signal T3 is memorized temporarily and then delivered. In such way, an organic connection is secured between three types of logic arithmetic means plus 1st, 2nd and 3rd temporary memory means, and these means are actuated rationally via the order signal. As a result, the number of the temporary memory means can be decreased, and thus the greater part can be shared in the operation outside and inside the parenthesis. |
