| 摘要 |
PURPOSE:To secure a large delay by utilizing the voltage lowering of an insulated gate field effect transistor (MOSFET) in a gate array using the MOSFET. CONSTITUTION:The gate electrode and source electrode of an N-type MOSFET 11 is connected to a +VDD which is the power potential of a positive electrode, a drain electrode is connected with the source electrode of a P-type MOSFET 12, and the source electrode of an N-type MOSFET 13 is connected to a -VSS which is the power potential of a negative electrode. The gate electrodes of the P-type MOSFET 12 and N-type MOSFET 13 are mutually connected, they are made into an input terminal 14 of an inverter circuit, the drain electrodes are also mutually connected, and they are made into an output terminal 15 of the inverter circuit. Consequently, by the voltage lowering of the N-type MOSFET 11, a potential impressed to the source electrode of the inverter circuit is lowered. Thus, the response speed of the inverter circuit is made slow, and a large delay time can be secured. |
