发明名称 FLIPPFLOP CIRCUIT
摘要 <p>PURPOSE:To secure a singular setting of the output signal level by transmitting the output signal of the main FF circuit to the auxiliary FF circuit in order to form the logic circuit along with the clock signal, the clear signal and others and then setting the output state of the auxiliary circuit. CONSTITUTION:Part of the output signal of auxiliary FF circuit 200 is fed back to main FF circuit 100. And the feedback signal, input signal, clock signal plus clear signal, reverse clear signal, preset signal or reverse preset signal are formed at N-channel serial-parallel circuits 107 and 122 plus P-channel serial-parallel circutis 114 and 129 of circuit 100. Then the output signal of circuit 100 is transmitted to circuit 200 to form the logic circuit along with the clock signal, clear signal or preset signal, and the output state is set for circuit 200 based on the state of the clear signal or the preset signal. As a result, the level of the output signal can be set singularly regardless of the clock signal and input signal.</p>
申请公布号 JPS5539474(A) 申请公布日期 1980.03.19
申请号 JP19780113341 申请日期 1978.09.14
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 SUZUKI YASOJI;TAKADA MINORU
分类号 H03K3/3562;H03K3/013;H03K3/356 主分类号 H03K3/3562
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