| 摘要 |
A control logic for linear sequence generators and ring counters to prevent "latch-up" in the "0" state having a linear sequence generator including a shift register with modulo-2 exclusive-OR feedback from the shift register to the shift register input and feedback through binary counters to detect and count n-1 consecutive "0"s in the shift register to feed a "1" into the shift register to prevent "0" state latch, where n is the number of shift register stages used.
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