| 摘要 |
<p>An integrated programmable logic arrangement is provided into which a logic pattern can be electronically written, and out of which a logic pattern can be electronically read-out. The logic arrangement has and ANDmatrix, and OR-matrix, switching transistors in the AND and OR matrices comprosing MI1I2S (metal-insulation 1-insulation 2-semiconductor) storage type transistors, and decoder means connected to the AND and OR matrices.</p> |
