发明名称 Input stage using junction field effect transistors for biasing
摘要 In a bias circuit including at least a pair of bipolar transistors interconnected to function as active loads, two junction field effect transistors are interconnected such that the source of one transistor is connected to the emitter of the first of the pair of bipolar transistors and the source of the second junction field effect transistor is connected to the emitter of the second of said bipolar transistors, and the gate electrodes of the first and second junction field effect transistors are electrically connected to each other and to the drain electrodes of both the first and second junction field effect transistors. Alternatively, the drain electrodes of the first and second junction field effect transistors are connected to a common bus and the gate electrodes are connected to a low impedance node.
申请公布号 US4194136(A) 申请公布日期 1980.03.18
申请号 US19770807602 申请日期 1977.06.17
申请人 FAIRCHILD CAMERA AND INSTRUMENT CORP 发明人 BUTLER, JAMES R
分类号 H03F3/45;(IPC1-7):H03K17/00 主分类号 H03F3/45
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