MULTIPLE MASK REGISTERS FOR SERVICING INTERRUPTS IN A MULTIPROCESSOR SYSTEM

摘要

Multiple mask registers located in a system communication controller enable each processor in a multiprocessing system to be a control processor and thereby select and execute interrupts on a priority basis. An executive program which supervises a processor loads its mask register with information according to the priority of the operation to be performed by the processor to control the answering of communication from itself and other modules of the processing system. The system controller includes an interrupt cells register associated with all of the mask registers. The interrupt cells store the existence of an interrupt request and are arranged in a predetermined priority which is altered by each mask register for each control processor.