| 摘要 |
PURPOSE:To enable a counter circuit to operate stably without reference to the initial states of D type FF circuits, by using AND signals of D type FF circuits next to the counter circuit as data signals of FF circuits before and after them. CONSTITUTION:To attain 2N-1 counting operation by cascading the N-number (D-FF) circuits 11 to 15 in loop, the Q output of D-FF15 is connected to reset terminal R of D-FF11, the output of inverter 16 is connected to data terminal D, and other D-FFs 12 to 15 are so connected that their D terminals will connect to respective Q terminals of prior stages; and the Q terminal of D-FF14 and the Q terminal of D-FF15 are connected to the input terminal of AND circuit 18 by way of NAND circuit 17 together with the Q terminal of D-FF12, and the output of AND circuit 18 is to the D terminal of D-FF13. Once a certain number of clock signals arrive at the CP terminal of D-FF11, each D-FF circuit resets without reference of its initial state. |
