| 摘要 |
PURPOSE:To avoid reading of the erroneous information and thus to enhance the reliability for the data transmission device of the cyclic digital transmission system by setting the input information after the variation of the input signal becomes steady. CONSTITUTION:The variation is detected for input signals 5-7 via state variation detection circuit 13, and the output is applied to timing circuit 12 by actuation of timer 14. The output of timer 14 is set to the time during which the time dispersion of the input signals can be absorbed, and circuit 12 inhibits reed clock rcl to be applied to buffer memory 11 via the output of timer 14. In other words, the setting of the input is inhibited to memory 11 within a fixed time after occurrence of the state variation, and the input is set to memory 11 after the variation of the state becomes steady to be then delivered through parallel-serial conversion circuit 15. In such way, the reading of the erroneous information can be prevented. |
