发明名称 ERROR CORRECTING PROCESSOR
摘要 PURPOSE:To make error corrections without interrupting a process if a two-bit error does not exceeds one byte, by correcting a multi-bit error by a one-byte block corrector. CONSTITUTION:Data from CPU are set to write data register WDR and also written into memory unit MSU, and check byte generator CG generates check bytes C1 and C2, which are written into memory unit MSU. In read operation, multiplexer MPX inputs the data to error detector ED equipped with the syndrome generator and error decision unit and if an error detected, it is corrected by data regenerator EC. Further, its result is passed through multiplexer MPX and error detector ED to makes a check on that data regenerator EC is operating accurately, thereby sending data out to CPU via read data register RDR.
申请公布号 JPS5533278(A) 申请公布日期 1980.03.08
申请号 JP19780106490 申请日期 1978.08.31
申请人 FUJITSU LTD 发明人 ARAYA OSAMU;KAMIYANAGI YUTAKA
分类号 G06F11/10;G06F12/16;G11B5/09;G11B20/18;G11C29/00;H03M13/00 主分类号 G06F11/10
代理机构 代理人
主权项
地址