| 摘要 |
PURPOSE:To ensure a steady counting action with no disturbance for a higher integration by interrupting the output of the initaializing gate into the input of the gate to be applied with the reverse clock pulse within the logic circuit at the subsequent step. CONSTITUTION:Initializing gate GR, which uses the output of 3rd and 4th gates G33 and G44 receiving application of clock pulse reverse CP in the 1st- and 2nd-step logic circuits plus pulse reverse CP as the input, is installed, and the output of GR is interrupted forcedly into the input of 4th gates G24 and G14 to which the pulse reverse CP in the 4th- and 5th-step logic circuits are applied. With installation of such simple-structure intializing means, a steady counting action can be secured with no disturbance for a higher integration. |
