发明名称 MEMORY UNIT
摘要 PURPOSE:To remove an intermittent error of two-bit error data by making a reread by making use of the two-bit error detecting function of an error detecting correction circuit. CONSTITUTION:When error detecting correction circuit 3 detects a two-bit error on signal line 102, an address corresponding to this two-bit error data is selected by address selector circuit 6 under the control of signal line 103 since this address is stored in address stand-by register 5, thereby realizing a reread from memory circuit 1. In this way, at most one bit of the two-bit error of data read out firstly is removed and when the other is caused by an intermittent read error, this intermittent error can be removed by rereading.
申请公布号 JPS5532230(A) 申请公布日期 1980.03.06
申请号 JP19780103644 申请日期 1978.08.25
申请人 NIPPON ELECTRIC CO 发明人 HANATANI SHIYUUICHI
分类号 G06F11/10;G06F12/16;G11C29/00 主分类号 G06F11/10
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