发明名称 MEMORY CONTROL SYSTEM
摘要 PURPOSE:To eliminate the need of the replacement of a component of a main memory even if, a fault occurs to the memory, by providing an error memory and substitute memory. CONSTITUTION:When an uncorrectable error occurs and error address Ej is detected, processor 5 writes ''1'' on disabling bit 12 of address Ej under the control of microprogram 4 and also writes ''1'' on substitute bit 11 of address Ej+1 while writing substitute address Aj of substitute memory 3 in address Ej+1. After the execution of arithmetic of Aj+2 to Aj and i+1 to i, the error bit in address (i) of error memory is set to ''1'' and error address Ej is stored. Therefore, the replacement of a component of the memory is unneded even if the main memory gets out of order.
申请公布号 JPS5532208(A) 申请公布日期 1980.03.06
申请号 JP19780102591 申请日期 1978.08.23
申请人 FUJITSU LTD 发明人 NOSAKA TAIJI
分类号 G06F12/16;G06F11/16;G11C29/00 主分类号 G06F12/16
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