| 摘要 |
<p>An apparatus and method for identifying faults in a digital logic circuit system (26) combines the output of a feedback signature generator (14) and synchronous transition counter (16) to provide a unique signature which is sensitive both to bit pattern timing and bit pattern sequence. A plurality of output signals via signal lines (32) of the circuit system (26) which are produced in response to a preselected input signal pattern of a test signal generator (24) is processed synchronously under control of a sequence controller (38) through a feedback signature generator (14), such as a serial cyclic redundancy check (CRC) network, and a synchronous bit transition counting network (16). A preselected portion of the output of the bit transition counting network (16) is combined via a signal line (82) with a preselected portion of the bits of the feedback signature generator (14) to obtain a pseudo-random characteristic output bit pattern, or signature, which is unique to the circuit system (26) under test. The fault detecting capability approaches one hundred percent with an embedded indication of the input test pattern duration as verification. </p> |
