发明名称 Single slope A/D converter with sample and hold
摘要 A converter circuit employs a capacitor coupled through a selector switch to an analog voltage so that the capacitor is charged to the analog level. When a conversion is commanded, the capacitor is disconnected from the analog voltage and discharged through a constant current load. This results in a linear voltage ramp. A comparator senses the capacitor voltage and compares it to a reference level that is slightly above ground. Upon starting the ramp an increment of voltage slightly larger than the reference is applied in series with the capacitor. When the ramp drops below the reference level the comparator output is used to terminate the conversion interval. Thus, the conversion interval is directly and linearly proportional to the magnitude of the analog voltage. If desired, the conversion interval can be used to operate a counter to provide a conventional digital readout. Alternatively, the device can be operated by a microprocessor with the readout being sensed and displayed if desired by the microprocessor. Due to the increment of voltage, the zero analog voltage conversion interval is a fixed finite time.
申请公布号 US4191942(A) 申请公布日期 1980.03.04
申请号 US19780913632 申请日期 1978.06.08
申请人 NATIONAL SEMICONDUCTOR CORP 发明人 LONG, DAVID K
分类号 H03M1/00;(IPC1-7):H03K13/02 主分类号 H03M1/00
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