| 摘要 |
PURPOSE:To simplify the circuit constitution, by making unnecessary the monostable circuit and the delay circuit, through the formation of the timing signal of the sample hold circuit for composite signal in synchronizing with the subcarrier with a simple frequency demultiplier and gate circuit. CONSTITUTION:The output frequency 152 KHz of the voltage controlled oscillator 5 of the PLL circuit taking the pilot signal in the stereo composite signal as reference input is demultiplied with the demultiplier 6 to output the frequency 75 KHz and also the frequency 38 KHz demultiplied with the demultiplier 7. The frequency division of the demultipliers 6 and 7 is in synchronizing with the duty pulse of frequency 152 KHz, the output of the demultipliers 6 and 7 and the oscillator 5 are fed to the gate circuits 11 and 12, timing signal is given to the sample hold circuit 13 when full input is fed with the circuit 11, and timing signal is given to the sample hold circuit 14 when full input is inputted at the circuit 12. Further, composite signal is in sample hold at the circuits 13 and 14 to output the signals L and R to the output. |
