| 摘要 |
PURPOSE:To enable to keep output continuously for the sample value, by stopping the sampling through the detection of the abnormal pulse included in the composite signal and to avoid the effect of the abnormal pulse included in the sampling output. CONSTITUTION:The signal in output frequency 152 KHz of the voltage controlled oscillator 9 of the PLL circuit 5 is in synchronizing with the trailing synchronism of the frequency 152 KHz with the demultipliers 10 and 11 to output the frequencies 76 KHz and 38 KHz. The output of the demultipliers 10 and 11 and the oscillator 9 are fed to the NAND circuits 20 and 21, which produce the first and second sampling timing pulses. The pulses operate the sample hold circuits 22 and 23 to sample hold the composite signal. The circuits 20 and 21 with this constitution are provided with the abnormal pulse detection circuit 15 which detects the abnormal signal included in the composite signal by taking the composite signal as an input. The circuit 15 stops the operation of the circuits 22 and 23 when the abnormal pulse is detected with the circuit 15 to avoid the invasion of the abnormal pulse. |
