Synchronisation system for binary signal receiver - has bistable flip=flops clocked by received signal and clock generator for producing comparison pulse

摘要

The system synchronises the reception of binary data using a divider chain driven by two different clock frequencies. A control circuit is synchronised to the clock generator and contains three bistable flipflops and a logic circuit. A comparator contains a first bistable flip flop clocked by the received signals, a second bistable flip flop clocked by the clock generator, and a logic circuit. The control circuit's logic comprises two AND-gates, and OR-gate and one NOR-gate.