Simplified digital multiplier for computers - uses parallel fed multiplicand(s) and partial multipliers with hard wired adders

摘要

The binary multiplier consists of a number of processing stages (V1-3) to which multiplicands (xO, x1, x2) are fed in parallel. Also fed to these stages are both digits of the 2-digit partial multipliers (y5, y4, . . . yo). Each unit has two sets of AND-gates (UO-U5). One input of the AND-gate is fed from a multiplicand, the other input being fed from a multiplier. The outputs of the processing stages are fed to a summing circuits (epsilon). A further adder (epsilon 12) is fed to a further adder (123) together with the sum result from the third intermediate adder (S3). As the respective shifts of the significant places at all the adder inputs are known in advance, these connections can be hard-wired, e.g. V1-V3, S2, S3, S12 and S123, leading to considerable simplification. Standard arithmetic modules in the form of integrated circuits can be used for the adders.