发明名称 |
Semiconductor overload protection structure |
摘要 |
An input voltage overload protection semiconductor structure useful with MOS circuitry consists of a p-region in an n-substrate with p+ type regions formed on both sides of the p-region and an n+ type region centrally located in the p-region. Input signals are applied to the first p+ region. The gate of an MOS structure to be protected from voltage overload is connected to the second p+ type region. A power supply used with the MOS structure is connected to the n+ region. This structure provides significantly greater load protection than the standard resistor-diode-resistor circuit.
|
申请公布号 |
US4189739(A) |
申请公布日期 |
1980.02.19 |
申请号 |
US19780884414 |
申请日期 |
1978.03.08 |
申请人 |
BELL TELEPHONE LABORATORIES INC |
发明人 |
COPELAND, JOHN A |
分类号 |
H01L27/02;(IPC1-7):H01L27/02 |
主分类号 |
H01L27/02 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|