发明名称 PARALLEL AUTOMATIC TEST SYSTEM
摘要 PURPOSE:To enable parallel test for a plurality of tests, by incorporating the memory section of the recognition data in the unit. CONSTITUTION:First, the information related to test is inputted from the operational panel OP. This operation drives DATACONT to read out test data corresponding by the information transfer control section INFTCONT, information transfer is made to the common control section COM and the input and output control section IOCONT to start the test sequentially. From the test unit finished earlier, interruption is made to the interruption reception section INTREC to inform the end of test. INTREC informs it to the analysis section ANLU. ANLU receives the information of the result of test via IOCONT to discriminate whether the test is good or not. In case of a failure, ANLU performs print control of the failure via the printer control section PRTCONT. Further, ANUL performs the write-in processing of information of the result of test to the corresponded test data storage section DATA by driving DATA-CONT via INFCONT.
申请公布号 JPS5521688(A) 申请公布日期 1980.02.15
申请号 JP19780095548 申请日期 1978.08.04
申请人 NIPPON ELECTRIC CO;NIPPON TELEGRAPH & TELEPHONE;OKI ELECTRIC IND CO LTD;HITACHI LTD;FUJITSU LTD 发明人 CHIBA MASAYASU;TANAKA TOSHIO;SAKAZUME WATARU;SHIMADA JIROU;UMAGAMI MASAO
分类号 H04M3/26;H04M3/22 主分类号 H04M3/26
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