| 摘要 |
PURPOSE:To improve a frequency characteristic by permitting a high speed operation with a reduced pattern area of SITL, a reduced gate capacitance of SIT together with increase of a conversion conductance. CONSTITUTION:A gate 24a is surrounded with a gate 23a under a drain mainly when the gate 23a is sustained at a low potential or a cavity extending from the gate 23a and suplimentary region 23c to a N-type semiconductor region to be isolated electrically from a drain substrate 21. When the gate 23a is sustained at a high potential, the cavity from the gate 23a is contracted, and a conduction path is occurred between the drain and substrate to turn a SIT to a conductive condition. |
