| 摘要 |
PURPOSE:To speed up the operation by performing the process only with the upper rank bits limited, in the unit in which division is made with the processing of multiplication for the approximate value Dt<-1> which is a reciprocal of the divisor D. CONSTITUTION:The X input corresponding to the value Q(j), Y input corresponding to the value dt and the remainder R(j) are inputted to the multiplication processing section 1, and the carry output C of the multiplication corresponding to the left side of equation (1) and the sum output S are respectively set to the registers 2 and 3. The upper rank bit of the outputs C and S is fed to the addition processing section 4 to obtain the step quotient Q (j+1). On the other hand, the remainder R(j+1) at that time is returned to the processing section 1 from the registers 2 and 3. The remainder processing section 6 repeats specified processing to obtain the final remainder at the remainder generator 9. The quotient generator 5 integrates the step quotients Q(O)... obtained every step. The processing speed can be increased by limiting the number of processing bits at the processing section 4. |
