Data processing system having centralized nonexistent memory address detection

摘要

In a data processing system which includes a central processing unit (CPU) having one or more common buses to which one or more main memory units for storing program software instructions and program data are connected, logic is provided within the CPU for detecting an attempt to access a main memory location not contained in the one or more main memory units present in the data processing system. Logic is provided for detecting the attempt to access the nonexistent memory location for the case where the access was being done in the course of the CPU executing a software instruction or for the case of where the access was being done to transfer data between the main memory and an input/output controller connected to one of the one or more common buses.