| 摘要 |
<p>A data bus system is disclosed which includes a plurality of interconnected active terminals (1, 2, 3, 4), i,e., terminals which receive serial data from one terminal and retransmit it or transmit new data to another terminal. The data is transmitted within a continuous series of time frames of predetermined length with each time frame being initiated by a control word transmitted by one of the terminals designated the controller terminal (e.g. 1 or 3). Each terminal includes a counter which counts the bits between control words, and each control word identifies the controller terminal so that each terminal can synchronize its counter with the counter at the controller terminal in accordance with the propagation time of data from the controller terminal. Logic circuitry at each terminal enables one (e.g. 1 or 3) of a plurality of the terminals to assume the function of the controller terminal should the presently designated controller terminal fail to generate control words. The system can therefore continue to operate in the event of partial interruption of the bus. Within each time frame, the terminals initiate data at times in accordance with the counts of their counters, and the transmitted data identifies each receiving terminal which directs it to users tied to that terminal.</p> |
