发明名称 CHROMINANCE SIGNAL PROCESSOR
摘要 PURPOSE:To obtain a processor which is high in general-purpose use and allows demodulation of a low-band conversion chrominance signal by generating timing for separation of a color difference signal from the demodulation axis of the low-band conversion chrominance signal by a relatively simple digital circuit. CONSTITUTION:A low-band conversion chrominance signal (q) inputted from a terminal 1 is A/D-converted in timing of a clock (b) by an A/D convertor 5, and added to a code inversion circuit 6, where only a minus component among color different signal components is code-inverted in timing of a code inversion pulse (f), and supplied to latch circuits 7a and 7b. In the latch circuits 7a and 7b, color-difference signal separating pulses q1 and q2 are latched, and two color different signal data d1 and d2 are separated from said pulses. The color difference signal separating pulses q1 and q2 delay the code inverting pulse (f) by one clock through a flip-flop 14, and are generated through an exclusive OR circuit 15 and a flip-flop 16.
申请公布号 JPS60136492(A) 申请公布日期 1985.07.19
申请号 JP19830249404 申请日期 1983.12.24
申请人 MATSUSHITA DENKI SANGYO KK 发明人 NAKAGAWA YUKIO;TOMITA MASAO;MATSUMOTO TOKIKAZU
分类号 H04N9/84;H04N9/78;H04N9/83;H04N9/87 主分类号 H04N9/84
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