| 摘要 |
PURPOSE:To cope with even a multi-input logic variable while securing perfect fail- safe quality, by arranging respective logic elements in parallel. CONSTITUTION:While arithmetic fA=x.y is performed by logic element A, arithmethic of (f ) is carried out not by f =x .y +x .y+x.y but by f = x .y +(x+y)(x +y ); arithmetic of the 1st member of x .y is performed by logic element B(fB= x.y ) and arithmetic of the 3rd member of x.y and the 2nd member of x .y is by logic elements AB1 and AB2 respectively. Then, respective logic elements are arranged in parallel on the whole. Consequently, the essential diode circuit of a conventional fail-safe logic circuit can be omitted, so that there will be no possibility of a fail-safe loss attending on the short of a diode. |
