发明名称 PROCESSOR OF TIME DATA
摘要 PURPOSE:To simplify the constitution of a circuit, by reducing the number of bits by processing time data by a binary code. CONSTITUTION:When making a modifying switch 19 after setting the desired modifying time by means of a digital switch 13, the output of the switch 13 presets a binary coded decimal down counter 14 by the differential output while setting a FF16, and further resets a frequency divider 2 and a binary counter 3. Clock pulses from the frequency divider 2 are fed to counters 3, 14 because a gate 17a is opened by the output of the FF16, the content of the counter 3 becomes to the desired time set when the content of the counter 14 becomes zero, the FF16 is reset by the output of the counter 14 at that time and this circuit is returned to the ordinary condition. Thus, time can be modified by the simple constitution of the circuit.
申请公布号 JPS5516252(A) 申请公布日期 1980.02.04
申请号 JP19780089028 申请日期 1978.07.21
申请人 SEIKOSHA KK 发明人 ISHIKAWA MORIAKI
分类号 G04G15/00;G04G13/00;G04G13/02;G04G99/00 主分类号 G04G15/00
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