| 摘要 |
In a circuit for selectively limiting the rate of change of an interference signal superimposed on a wanted signal, the composite signal Es is fed to a shaping circuit comprising a feedback path which includes an integrator J1 having a variable integration time determined by adder A2, sample and hold circuits S1 and multiplier M1. The resulting signal ???Es is the interference signal and, after having any d.c. component removed by sample and hold circuit S2 and adder A5, has its slope compared with a reference slope in adder A6 to generate a "0" or "1" signal at II depending on whether the rate of change on ???Es is less or greater than the reference slope. The signal controls a changeover circuit M2, M3, A4 so that ???Es is passed to output AS directly if the rate of change low and via a delaying and slope limiting circuit ZV if it is high. <IMAGE> |
