| 摘要 |
PURPOSE:To ensure generation of the demodulated carrier wavs which is free from fluctuation by presuming the demodulation carrier phase jitter caused by the sampling clock jitter from the control information of the digital phase lock loop and then offsetting the jitter. CONSTITUTION:The carrier band signal sent from terminal 1 is sampled by sampler 3 and with clock 2 and then demodulated by synchronous detector 6 via A/D converter 4 and also converted into the sampling phase information via square element 7 and filter 8. Thus digital phase lock loop 10 is controlled. And the expected value of the date is delivered through decision unit 11 from the base band signal sent from detector 6. The phase error obtained from phase error detector 12 is added with the constant-fold signal of the sampling phase signal through through adder 14 and via loop filter 13 to the applied to intergrator 16. The output of integrator 16 controls voltage control oscillator 17 via the modulation carrier phase control signal from which the effect of the sampling clock phase is eliminated. |
