System for resetting the operation of a signal processing device upon the failure of accessng a predetermined memory location within a predetermined time interval

摘要

Fault tolerant operation of a microprocessor-based control system is provided by proper execution of an operating program stored in a read only memory (ROM) by a central processing unit (CPU), or microprocessor/microcomputer, as determined by monitoring program access of a select memory location within the ROM. Failure to access the select memory location within a designated time period indicates improper CPU operation and allows a shift register to output a reset signal to automatic reset circuitry for reinitializing CPU operation. The automatic reset circuitry monitors CPU operation and continually attempts to reset the CPU until proper resetting thereof is accomplished. A visual and/or aural indication of CPU reset as well as the number of times it is reset is provided to an operator. The CPU is coupled to a host computer for indicating to the host computer that the CPU has been reset and is now ready to receive data from the host computer. The present invention is particularly adapted for use in the headend of a cable television (CATV) system for ensuring proper operation of a CPU used to control program decoders and subscriber encoders, but is not limited in its application to this environment as it has application in any microprocessor-based control system.