发明名称 INFORMATION PROCESS SYSTEM
摘要 PURPOSE:To prevent the system-down for the multi-processor system caused by the same machine check error in case the memory error takes place at the main memory, by adding the error processor and the submemory. CONSTITUTION:In case the memory error is detected through error detection circuit 3 when the request is given to main memory 1 from muCPU1, memory error announcement (a) is produced to error processor 7. Processor 7 checks with which muCPU's reference data the error is produced, and then gives forcedly jump order (d) to be given to the error process routine to the referred muCPU. At the same time, memory freezing signal (c) is sent to priority acceptance circuit 4 to freeze temporarily memory 1 and thus to inhibit the acceptance excepting the microprocessor which carries out the error process. On the other hand, muCPU1 carries out the memory error process via submemory 8.
申请公布号 JPS5513440(A) 申请公布日期 1980.01.30
申请号 JP19780085100 申请日期 1978.07.14
申请人 HITACHI LTD 发明人 HINO YUUSUKE
分类号 G06F11/18;G06F11/00;G06F12/16;G06F15/16 主分类号 G06F11/18
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