发明名称 CONTROL SYSTEM FOR MULTIPLEX MEMORY UNIT
摘要 PURPOSE:To speed up more the accessing to the momory unit, by transmitting two different adresses to the duplex memory unit, when CPU makes readout operation. CONSTITUTION:When the CPU 4 performs readout operation, two different address are transmitted to the duplex memory unit 3. For example, continuous addresses alpha and alpha+1 are simultaneously accessed. The unit 3 accesses the address alpha to one system and the address alpha+1 to another system. If no error is detected to the data in two words read out, the two words are transmitted to the CPU 4 simultaneously. Further, if any error is detected in the data read out with the access to the address alpha of the memory 1, access is made to the address alpha of the memory 2. Further, error restoration is made by writing in the memory content at the address alpha of the memory 2 to the address alpha of the memory 1.
申请公布号 JPS5512533(A) 申请公布日期 1980.01.29
申请号 JP19780083997 申请日期 1978.07.12
申请人 HITACHI LTD 发明人 NOGUCHI SEKIKEN;IDE TOSHIYUKI
分类号 G06F12/16;G11C7/00;G11C29/00 主分类号 G06F12/16
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