| 摘要 |
PURPOSE:To obtain an amplifer circuit featuring the excellent voltage reduction characteristics by using the FET's for amplification and load use plus the resistance and the diode connected in parallel between the power source and the base of transistor Tr which supplies the bias to the Tr amplifying the output of the FET. CONSTITUTION:Input signal 301 is amplified by amplification FETT5and load FETT6, and the output is applied to the base of bipolar TrT7 to be delivered through terminal 302 connected to the collector after amplification. The emitter of TrT7 is connected to the power source via resistance R12 and R11. The connection point of R12 and R11 is connected to the emitter of TrT8, and the parallel circuit comprising diode D1 and D2 plus resistance R14 is connected between the base of T8 and the power source and with resistance R15 connected between the base and the earth. Now if the balue of R14 and R15 are set so that the voltage at base point (a) of T8 may be VP when the power voltage becomes 2VP of pinch- off voltage VP of FET, the power voltage is reduced down to the value of 2VP. During this period, FETT5 and T6 operate at the saturation region, thus obtaining an amplifier featuring a high voltage reduction characteristics. |
