| 摘要 |
The converter comprises a data source (10) from which half-bytes of data are supplied in a parallel-by-bit, serial-by-half-byte manner to data registers (14, 16). The supply is controlled by control logic (18) so that register (14) is being filled while register (16) is being emptied and vice versa. Data from the registers (14, 16) are supplied to steering circuits (28, 30, 32, 34) which act as gating circuits. Circuits (28, 30) are gated by a first signal taken from counter (20) and circuits (32, 34) by a second signal taken from the counter. The first and second signals are in anti-phase and are operative so that in one quarter cycle bits (0, 1) are gated through circuits (28, 30); in the second quarter cycle bits (2, 3) are gated through circuits (32, 34); in the third quarter cycle bits (4, 5) are gated through circuits (28, 30); and in the fourth quarter cycle bits (6, 7) are gated through circuits (32, 34). The sample and interleave circuit (36) receives the signals gated through circuits (28, 30, 32, 34) and is operative, under the control of sample (A, B, C, D) timing signals, to sample and gate to a common output line, the outputs of the circuits (28, 30; 32, 34; 28, 30; 32, 34) during the four quarter cycles, two sampling being made serially every quarter cycle. |
