| 摘要 |
<p>In a circuit arrangement wherein a memory matrix and an address decoder are constructed of ROMs, a semiconductor read only memory is characterized in that at least he address decoder ROM, in which the number of output lines to be selected is smaller than the number of non-selected output lines is constructed in accordance with a longitudinal system in which a plurality of MISFETs are connected in series between respective output lines arrayed in the column direction and a reference voltage terminal. The MISFETs form a desired pattern in the row direction, and current is permitted to flow through only a load MISFET connected with a selected one of the address select lines.</p> |
