| 摘要 |
PURPOSE:To secure an economical reproduction of the timing information for sampling from the reception signals through a digital process for the digital receiver by detecting the sampling position to the reception digital signals with correction. CONSTITUTION:Output signals SL1 and SL2 which are obtained by giving the delay of 1/2Tb and Tb to reception data signal SSX of transmission cycle Tb via delay circuit DL are compared with each other through exclusive OR gates E1-E3. And in case no agreement is obtained, the logic 1 signals are supplied to AND gates A1 and A2. When both input feature logic 1, the output of the AND gate becomes logic 1 and then drawn into FFD1 or D2 with the rise of clock signals SOSC which are formed into the timing information used for sampling of the reception signals of voltage control oscillator OSC. And in case the sampling phase shows an advance to signal SSX, the output of D1 is supplied to oscillator OSC; while the output of D2 is supplied in case the sampling phase shows a delay respectively. The frequency or the phase of OSC is controlled to form signals SOSC into the timing information featuring a small phase error. |
