发明名称 HARDWARE DEMAND FETCH CYCLE SYSTEM INTERFACE
摘要 A data processing system includes a central processor unit (CPU), a main memory and a memory management unit (MMU). Information is stored in main memory in segments, each segment being identified by a segment descriptor stored in a translation table in the MMU. Logical addresses from the CPU address segment descriptors in the MMU's translation table. These segment descriptors include the physical address of the location in main memory of the first word of the segment. If the segment descriptor is not in the translation table location, then the MMU operation is suspended while the segment descriptor is demand fetched from main memory.
申请公布号 CA1284387(C) 申请公布日期 1991.05.21
申请号 CA19870537353 申请日期 1987.05.19
申请人 HONEYWELL BULL INC. 发明人 SMITH, MICHAEL D.;DUNWELL, LLEWELYN S.;LEMAY, RICHARD A.;MILLER, ROBERT C.;STAPLIN, THEODORE R., JR.;WOODS, WILLIAM E.;CURLEY, JOHN L.
分类号 G06F9/00;G06F9/22;G06F9/30 主分类号 G06F9/00
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