发明名称 |
High yield processing for silicon-on-sapphire CMOS integrated circuits |
摘要 |
Described herein a technique for constructing a complementary MOS device on a sapphire substrate so that the surface of the device is planarized, the P-channel and N-channel devices are in substantially correct registration, the threshold voltage for the back-channel leakage effect inherent in sapphire substrate device to occur is increased, and the areas of gate oxidation are pseudo self-aligned so as to minimize overlap of the gate oxide with the source and drain regions.
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申请公布号 |
US4183134(A) |
申请公布日期 |
1980.01.15 |
申请号 |
US19780968529 |
申请日期 |
1978.12.11 |
申请人 |
WESTINGHOUSE ELECTRIC CORP |
发明人 |
CRICCHI, JAMES R;HERMAN, DAVID S;OEHLER, HARRY G |
分类号 |
H01L21/32;H01L21/762;H01L21/86;H01L27/12;(IPC1-7):H01L21/22;H01L21/26 |
主分类号 |
H01L21/32 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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