发明名称 LOW FREQUENCY DELAY CIRCUIT
摘要 PURPOSE:To obtain a delay clock with a waveform having no disturbance and with a desired duty ratio by delaying an input clock by a desired time through the operation in a short time. CONSTITUTION:The low frequency delay circuit giving an optional delay to an inputted clock and outputting the delayed signal consists of a delay generating means comprising a 1st monostable multivibrator 14 outputting a lock whose pulse width depends on a time constant upon the receipt of the clock, a 1st capacitor being one factor of the time constant and a 1st variable resistor means 15 varying the said time constant by varying its resistance, and of a duty ratio correction means comprising a 2nd monostable multivibrator 19 receiving a delay clock whose pulse width depends on a time constant upon the receipt of the clock from the said 1st monostable multivibrator, a 2nd capacitor being one factor of the said time constant and a 2nd variable resistor 20 means varying the said time constant by varying its resistance.
申请公布号 JPH04219014(A) 申请公布日期 1992.08.10
申请号 JP19900410101 申请日期 1990.12.13
申请人 FUJITSU LTD 发明人 SASAKI HIROSHI
分类号 H03K5/13 主分类号 H03K5/13
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