发明名称 INPUT*OUTPUT PROCESSOR
摘要 PURPOSE:To avoid the effect to be given to the system even in case the priority means of the processor has breakdown, by providing the signal line between each channel and the common control part and then installing there the means to send out the channel's operation state plus the means to detect the operation start of other channels. CONSTITUTION:Channels 21-2n are combined to common control part 1 via common bus 103; and if the combination request is given from part 1, the output corresponding to the request is detected by detecting means 14 provided within part 1 to decide the presence or absence of the fault. In other words, flip-flops 111-11n to display the operation plus signal lines 1011-101n to inform the operation state of one channel to other channels are provided each to each of channels 21-2n to be connected to means 14. Furthermore, in case other channels are going to have malfunction while one channel is under operation, signal line 102 is provided to inform this. Then signal sending means 131-13n are connected to line 102 in order to secure the smooth operation for the system.
申请公布号 JPS553037(A) 申请公布日期 1980.01.10
申请号 JP19780075021 申请日期 1978.06.20
申请人 NIPPON ELECTRIC CO 发明人 KANEKO HIDEO
分类号 G06F11/00;G06F3/00;G06F11/28;G06F13/00 主分类号 G06F11/00
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