Shift register unit controlled by clock pulse - counts bits of data words received and signals number of free locations

摘要

Theunit has at least one shift register for storage of data words. Data words are fed into a first shift register until it is full. A detector signals each bit of a data word and the beginning and end of each series of data words. A counter controlled by the detector detects the degree of filling of the first register at the end of the series. A signal generator controlled by the counter delivers signals corresponding to the number of storage locations still free in the shift register.