| 摘要 |
PURPOSE:To surely prevent the abnormal operations of a microcomputer and to evade the malfunction of a controlled object by switching a clock signal to a divided clock of low frequency when the power voltage drops. CONSTITUTION:A voltage monitor circuit 41 detects it when the power voltage +VCC drops less than s prescribed level and outputs a drop detection signal VD. The signal VD is inputted to a switching circuit 44 and sets an F/F 46. When the F/F 46 is set, an AND gate 49 of the circuit 44 is closed and an AND gate 48 is opened. Thus a frequency divided clock signal CK1 is inputted to an input terminal CK of a microcomputer 31 through the gate 48 and an OR gate 50. Meanwhile the signal VD is inputted to a microcomputer 31 as an interruption signal. Then the microcomputer 31 activates an interruption processing program and carries out the fault countermeasure processing synchronously with the signal CK1. When this processing is complete, an F/F 51 is reset and then the microcomputer 31 is forcibly reset. |
