| 摘要 |
1. Precision decoder decoding the first pulse of a pair, comprising a shift register (2) continuously activated by a clock signal of the frequency F and receiving the pulses to be decoded, means (6) for defining a decoding tolerance window, a multiplexer (5) for selecting one output of the shift register in accordance with the interrogation mode used, a coincidence decoding gate (7) for receiving the output signals of the means for defining a tolerance window and of the multiplexer and providing a decoded pulse (ID) indicating the decoding of a pair when these signals are in coincidence, characterised in that it further comprises : - a clock (4) providing a primary clock signal of the frequency f determined by the desired precision ; - a first binary counter (3) having n bistables for dividing the primary clock signal by k(k=2**n ) and providing a secondary clock signal of the frequency F the precision of which is inferior to that of the primary clock, and which is the clock signal applied to the shift register (2) ; - a second binary counter (10) having N bistables for counting down the periods of the secondary clock signal ; - a first register (8) for storing the content of the first counter (3) upon control of each pulse to be decoded ; - a read/write random access memory (9) having 2**N n bit bytes for storing the different successive contents of the first register (8) under control of the second binary counter the input of which provides the address of the word to be stored ; - a subtractor (12) for subtracting a number m+a determined by the sum of the interval between two successive pulses to be decoded and the width of the tolerance window from the content of the second binary counter (10) ; - a second register (11) for storing the result of said subtraction upon control of the decoded pulse (ID) and for controlling reading of the read/write memory (9) through an N bit word, indicating the address of the word to be read and representing the arrival moment of the first pulse to be decoded of the pair with the precision of the secondary clock signal ; and - a third register (13) for storing the n bit byte read from the read/write memory (9), this n bit byte completing the N bit byte for forming a word of N+n bits forming the output signal of the decoder and representing the arrival moment of the first pulse to be decoded of the pair with the precision of the primary clock signal.
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