| 摘要 |
<p>PURPOSE:To improve operability by employing an external address system corresponding to one memory space in which plural sub.memory cell arrays are logically connected during a data writing. CONSTITUTION:When data are written into a memory cell array 4, externally given addresses are decoded by a writing circuit 6 as external addresses and a data writing 4 for the array 4, to which sub.memory cell arrays 2a and 2b are connected, is executed. Thus, if '000H' to '7FFFH' addresses are assigned to a certain kind of data group A and '8000H' to 'FFFFH' addresses are assigned to a different kind of data group to which accesses are made asynchronous to the data group A during a programming, a data writing is accomplished in one operation. Since only one writing circuit is provided for all sub.memory cell arrays, the number of writing circuits is greatly reduced and the chip area is considerably reduced.</p> |
